1.
Setting Things Up
1.1.
Setting up the compiler
1.2.
Setting up the linker
1.3.
Setting up the Riscv Virtual environment
1.4.
Setting up the Build automation tool
2.
writing a bare metal Rust executable
3.
boot_design
4.
Boot Design
5.
The Bootloader
6.
The Bootloader_2
7.
Setting Up Communications
7.1.
Designs and layouts
7.2.
General Theory on communication
7.3.
The UART
7.4.
More About the UART
7.5.
Programming_the_UART
8.
Theory on Paging
8.1.
segmentation
8.2.
paging
9.
Setting Up Memory Management
10.
Designs
10.1.
The RAM Management
10.1.1.
Abstracting the RAM
10.1.2.
Allocating RAM Memory
10.1.3.
Byte-grained allocation
10.1.4.
Setting Up RAM Memory Virtualization and access_management
10.1.5.
Using the Physical MMU instead of Virtual MMU
10.1.6.
Actual_implementation
11.
Handling interrupts and Traps
12.
Handling interrupts and Traps 2
12.1.
Exceptions
12.2.
Timer_interrupt
12.3.
External Interrupt
12.3.1.
UART Interrupt
13.
Handling External Interrupts
14.
Setting up Processes
15.
Processes Version 2
16.
The Block Driver
17.
system_calls
18.
Filesystem
19.
User Processes
20.
Overall Design
21.
Definitions and Theories
21.1.
The linker
21.2.
Qemu
21.3.
fragmentation_issues
21.4.
Memory Tracking Mechanisms
21.5.
Theory on MMU implementation in Riscv
21.6.
VirtIO
22.
Miscellenious
22.1.
Error Numbers
22.2.
Measuring Performance of software
22.3.
Importing variables from the Linker script
22.4.
GNU assembly macros
22.5.
The singleton Structure
22.6.
Multitasking
22.7.
Bitmasking_and_bit_operations
22.8.
Compressed Instructions
22.9.
The ABI
22.10.
Elf Files
22.11.
Riscv_registers
22.12.
Virtual representation of riscv in Qemu
22.12.1.
PCIe express devices
22.12.2.
VIRTIO devices
22.13.
Global Allocator
22.14.
Falling_to_fly
23.
AfterMath
23.1.
buffer_overflow_attacks
23.2.
fork_bomb
24.
Web Assembly
24.1.
Literature review papers
24.1.1.
Software_deployment
24.2.
Setting Up Wasm Runtime
24.3.
webassembly_challenges
24.4.
The Book
24.5.
Using A Wasm Runtime in a no-std environment
25.
RISCV_RUN
25.1.
reasons_for_RISCV
25.2.
priviledged_architecture
25.3.
error_handling_in_machine_mode
25.4.
seperating_user_mode_from_machine_mode
25.5.
Supervisor_mode_to_the_rescue
25.6.
Learning_magic
25.6.1.
resources
25.6.2.
random_notes
26.
References
27.
Problem_statement
28.
Implementations
29.
Debugging in Rust
30.
Qemu Configurations
31.
Link Scripts
32.
Documentation
32.1.
mermaid
33.
Testing
33.1.
No-Std Testing
33.2.
Unit Tests
33.3.
Integration Tests
34.
Debugging
Light
Rust
Coal
Navy
Ayu
Developer Documentation
Overall Design
Here we have the Computer components
CPU(Hart0)
RAM
MMIO Memory
HDD Memory
Screen
Keyboard
PLIC (Platform Level Interrupt Controller)
CLINT (core Local Interruptor)
UART
Components